The invention relates generally to methods for providing isolation between adjacent regions of an integrated circuit and more particularly to methods of reducing current leakage from an active region to a field oxide region in a circuit, such as an image sensor circuit.
Complementary metal-oxide-semiconductor (CMOS) technology is used in the design and fabrication of integrated circuits for many types of applications. CMOS technology uses n-type transistors (NMOS) and p-type transistors (PMOS) that are formed by doping selected regions of a substrate and by forming layers on the substrate. A p-type material, such as boron, may be introduced to a bulk silicon substrate in a blanket ion implantation step. Field oxide regions and n-type regions may then be formed using well known integrated circuit fabrication techniques. Similarly, the processes for depositing conductive and dielectric layers on the substrate to complete the circuit are known.
One general area for applying CMOS technology that has received significant attention is image capture and processing. Imaging applications include video, still photography, and navigation that is based upon optical detection. Linear or two-dimensional arrays of pixels are formed along the surface of the substrate, with each pixel periodically generating a signal having a current or voltage level that is indicative of the intensity of light incident to that pixel. A typical three-transistor pixel 10 that is used in current CMOS image sensors is shown in FIG. 1. Sensors that use this technology are often referred to as CMOS active pixel sensors (APS). A timing diagram for the operation of the three-transistor pixel 10 is shown in FIG. 2. In typical operation, a node N1 is set to a predetermined voltage Vddxe2x80x2 (which may be different than the circuit operating voltage Vdd) by turning on an n-channel reset transistor 12. The state of the reset transistor is determined by controlling a reset voltage (Vreset) In FIG. 2, Vreset goes high at time T0, causing the node N1 to ramp to Vddxe2x80x2. At time T1, the reset transistor 12 is turned off and photoelectrons are generated by the incident light on a photodiode 14. The photoelectrons are injected into node N1, reducing the voltage on that node by a value of Vsense=Vddxe2x80x2xe2x88x92(Iphotoxc3x97Tilluminate/CN1). In this equation, Iphoto is the photocurrent induced by the incident light, Tilluminate is the illumination time period and CN1 is the capacitance on node N1. Both Vddxe2x80x2 and Vsense can in principle be read out of the pixel through a source-follower 16 by activating a row-select transistor 18. In a two-dimensional array of pixels, there typically are row-select transistors and column-select transistors that allow the pixels to be sequentially sampled. The row-select transistor 18 is activated by manipulating a row-select (RS) signal. The illumination on the pixel is then proportional to Vddxe2x80x2xe2x88x92Vsense=Iphotoxc3x97Tilluminate/CN1. Persons skilled in the art refer to this operation as Correlated Double Sampling (CDS). Sampling occurs at time T2 before Tilluminate and time T3 during Tilluminate. The pixel is reset at time T4, since Vreset is caused to go high.
One of the major problems of using CMOS technology in imaging sensors is the relatively large dark current intrinsic to the CMOS process. A significant cause of the large dark current is the reverse-bias diode leakage in the photodiode 14 of a pixel, as well as in the source diffusion of the MOS field effect transistor (MOSFET) 12 connected to the photodiode. The diode leakage is often dominated by the edge leakage currents. Furthermore, in deep-submicron generations of CMOS technology, this leakage current will only increase and take major engineering efforts to suppress.
The physical layout of the CMOS APS pixel 10 of FIG. 1 will be described with reference to FIGS. 3, 4 and 5. FIG. 3 is a top view of the circuit layout of the APS pixel of FIG. 1, showing the various layers and diffusion regions. FIG. 4 is a top view that isolates the active area diode of FIG. 3, while FIG. 5 is a side sectional view of FIG. 4. The active area diode is illustrated as being an n+/p diode fabricated in a p-substrate or p-well. However, the descriptions of the operations and problems apply equally to a p+/n diode in an n-substrate or n-well. The pn-junction of the diode 14 is defined by the p-substrate or p-well 20, which will be referred to as the p-layer. Electrical connections 22 and 24 to the diode are formed by depositing layers that are in contact with an n+ region 26 and a p+ region 28, respectively. The n+ region 26 may be formed by ion implantation or other doping techniques into the active area that is identified as the photodiode 14 in FIG. 3. The active area is delineated by a field oxide (FOX) region 30. Typically, the FOX region is a thick layer of silicon dioxide (SiO2) that electrically isolates the active area from other regions of the substrate, which is typically a silicon substrate. There are several well known processes for forming the FOX. Any of the processes may be used to form the FOX of FIGS. 3-5. However, each of the known processes is susceptible to the formation of a high density of defects at the edges of the FOX. The defects are primarily due to mechanical stress effects and contamination. The high density of defects located within the pn-junction diode""s depletion region contributes to the high reverse-bias leakage current found at the field-edge of the diode. There has been much research and development regarding providing process steps (such as oxide deposition, etching and annealing) that minimize the edge leakage. However, the edge leakage problem is expected to become worse as the CMOS process is applied at the deep-submicron level.
Referring specifically to FIGS. 1 and 3, the gates of the three transistors 12, 16 and 18 are formed by a patterned polysilicon layer. The polysilicon layer is identified by hatching in FIG. 3. The reset transistor 12 has a gate 32, the row-select transistor 18 has a gate 34, while the transistor 16 has a gate 36 that is electrically coupled to the N1 node 22. The source/drain regions of the three transistors are formed by diffusions using the appropriate dopants. As can be seen in FIGS. 1 and 3, the transistors 16 and 18 have source/drain regions that are formed by a common diffusion region 38.
Dark current in the CMOS APS pixel 10 with an active area photodiode 14 is caused mainly by the photodiode leakage, which bleeds charge from the node 22 (N1). This reduces the voltage on the node, even when the reset transistor 12 is turned off during the illumination time Tilluminate. Therefore, the diode leakage produces an offset in the differential voltage produced by the illumination, given by Vddxe2x80x2xe2x88x92(Iphoto+Idark)xc3x97Tilluminate/CN1. For low light illumination, it is possible for Idark to be approximately the same as Iphoto. Thus, the dark current limits the dynamic range of the image sensor. Dark current reduction has usually been addressed by attempting to lower the intrinsic diode leakage of the CMOS technology via processing steps. This minimization of the diode leakage characteristics is very difficult in advanced deep-submicron CMOS technologies that use advanced field oxide formation techniques and have much higher doping concentrations in the diode.
Field-edge leakage can also be a significant problem at the transistor level of the pixel 10. Each of the three MOSFETs 12, 16 and 18 is formed by growing a thin gate oxide over the active area of the transistor and then forming the gates 32, 34 and 36 by patterning strips of polysilicon over the thin gate oxide. The n+ dopant is implanted after the gates have been formed. For each transistor, two separate n+/p diodes are then simply the source and drain diffusions in combination with the p+ contact. Because the source and drain diffusions are delineated by field oxides on three sides, they have the same field-edge leakage problem as the isolated n+/p diode.
There have been attempts to isolate active components of two complementary transistors. One such attempt is described in U.S. Pat. No. 5,847,433 to Kerber, which is not related to imaging applications. In order to produce isolated active regions of a CMOS circuit, a field plate is formed and doped jointly with wells located between the field plate. Therefore, the field plate includes an n-doped region and a p-doped region, as well as a boundary region between the two doped regions. Each doped region is electrically connected to the well that is located beneath it. As a result, a flat band condition prevails at the substrate surface. While the Kerber method provides an improvement, dark current leakage is still a problem, particularly in imaging applications.
What is needed is an integrated circuit fabrication method that is applicable to imaging applications and that provides further reductions in the edge leakage component of diodes and source/drain diffusions of MOSFETs.
A fabrication method for providing isolation between regions of an integrated circuit includes forming a guard layer on a peripheral portion of at least one of two adjacent regions of a substrate, so that when dopant is introduced into the substrate, an intermediate transition strip is left substantially dopant-free. The transition strip inhibits current leakage from an active region to an adjacent region, which is preferably a field oxide region. In the preferred embodiment, the active region is an active area diode, such as the one used in an Active Pixel Sensor (APS) pixel. Also in the preferred embodiment, the guard layer is a conductive material that is connected to a source of a bias voltage. For an APS pixel, the biased guard layer blocks the doping of the active area diode during fabrication and effectively blocks edge leakage current during circuit operation, as long as the guard layer is biased below the threshold voltage of the MOS system in which it is formed. The use of some process technologies will require bias in accumulation.
In one embodiment, the guard layer is formed of a patterned conductive material (such as polysilicon) on the peripheral portion of the active region. The guard layer extends across the peripheral portion to at least the edge of the adjacent field oxide region. Optionally, the guard layer extends onto a peripheral portion of the field oxide region, thereby relaxing the alignment tolerances. The overlap of the guard layer onto the active area will depend upon factors such as the alignment specifications of the photo-lithography tools used in the fabrication technology, but will typically be about the same as the overlap of the guard layer onto the field oxide region, if such an overlap is utilized. Since depositing polysilicon is a standard part of a CMOS circuit, such a modification of the existing active area diode is relatively simple to accomplish.
In an alternative application, the guard layer is patterned conductive material that extends along the interface between a source/drain region of a MOSFET and a field oxide region. The dopant-free transition strip that is formed by using the guard layer as a shield in a subsequent step of introducing dopant into the source/drain region isolates the doped region from the field oxide region. In this embodiment, the guard layer is preferably formed of polysilicon and is simultaneously formed with and connected to the gate of the MOSFET. When the gate is biased to a high voltage (i.e., the MOSFET is turned on), there will be an inversion layer generated under the guard layer, thereby extending along the interface of the source/drain region and the field oxide edge. Optionally, the guard layer may be patterned about both of the source/drain regions. Connecting the polysilicon guard layer to the gate of the MOSFET has advantages with regard to fabrication simplicity. However, the practice may result in an unacceptable leakage level (due to the gate-edge leakage) and/or an unacceptable increase in source/drain capacitance. In addition, because of the standard overlap of the gate region onto the source/drain regions, gate-to-source/drain capacitance will increase. If the extra leakage or capacitance is problematic, it is possible to separate the gate polysilicon from the polysilicon guard layer. In this case, the polysilicon guard layer should be biased by another contact.
In a third embodiment, the guard layer is used for MOSFETs that share diffusions. MOSFETs that share a common diffusion are often used in CMOS circuits to lower the total layout area. By depositing the guard layer along the interface between an adjacent field oxide region and a common diffusion region, edge leakage is reduced. In this embodiment, the guard layer may be connected to one of the gates of the two MOSFETs, but not both, unless the two gates are tied to the same circuit node. For applications in which the two transistors are operated separately, the guard layer may be connected to one of the two gates or may be connected to a separate contact.
An advantage of the invention is that depositing the guard layer prior to introducing the dopant into an active region provides control over edge leakage without significantly diverging from existing fabrication techniques. In the preferred embodiment, the guard layer is formed of polysilicon that is formed at the same time as the gates of the transistors. The guard layer has the same thickness as the gates and preferably has the same width, but this is not critical.